Flat panel field emission displays (FPFEDs) are known. See, for instance, the report on page 11 of the December 1991 issue of Semiconductor International. See also C. A. Spindt et al., IEEE Transactions on Electron Devices, Vol. 36(1), pp. 225-228, incorporated herein by reference. Briefly, such a display typically comprises a flat vacuum cell with a matrix array of microscopic field emitter cathode tips formed on the back plate of the cell, and a phosphor-coated anode on the front plate of the cell. Between cathode and anode is a third element, frequently referred to as "grid" or "gate".
As is disclosed, for instance, in U.S. Pat. No. 4,940,916 (issued Jul. 10, 1990 to M. Borel et al., for "Electron Source with Micropoint Emissive Cathodes . . . ", incorporated herein by reference), the cathode structure typically comprises a multiplicity of individually addressable conductor strips, and the gate structure similarly comprises a multiplicity of individually addressable conductive strips that are disposed at an angle (typically a right angle) to the cathode conductor strips. Each intersection region defines a display element (pixel). With each pixel is associated a multiplicity of emitters (e.g., 10.sup.2 -10.sup.3 emitters/pixel), and associated with each emitter is an aperture through the gate, such that electrons can pass freely from the emitter to the anode. A given pixel is activated by application of an appropriate voltage between the cathode conductor strip and the gate conductor strip whose intersection defines the pixel. Typically a voltage that is more positive with respect to the cathode than the gate voltage is applied to the anode, in order to impart the required relatively high energy (e.g., about 400 eV) to the emitted electrons.
As is also disclosed in the '916 patent, FPFEDs can have a current-limiting resistor (18 of FIG. 3 of '916) in series with each cathode conductor strip. In order to avoid a problem attendant upon such an arrangement (namely, the fact that such FPFEDs frequently contain abnormally bright spots, due to the unavoidable presence of emitter tips of particularly favorable structure), the '916 patent teaches provision of a series resistor R.sub.i for each individual emitter tip, instead of current-limiting resistor 18. This is accomplished by interposition of a resistive layer (5 of FIG. 4 of '916) between the cathode conductor strip and the emitter tips thereon.
However, such an arrangement typically requires that many (e.g., about 10.sup.3) emitter tips be provided for each pixel, in order to avoid perceptible brightness variation if one or more of the emitter tips fails. This in turn results in relatively high capacitance per pixel, which in turn generally leads to relatively high power consumption.
In view of the considerable economic potential of FPFEDs, it would be highly desirable to have available a FPFED that is free of, or at least less subject to, the above discussed and/or other shortcomings of prior art FPFEDs. This application discloses such a FPFED.